As one of semiconductor device wafers, there is an SOI (Silicon On Insulator) wafer having a silicon layer (which may be referred to as an SOI layer hereinafter) formed on a silicon oxide film as an insulator film. This SOI wafer has characteristics such as a small parasitic capacitance or a high radiation-proof capability since the SOI layer in a substrate surface layer portion that functions as a device fabrication region is electrically separated from the inside of the substrate by, e.g., a buried insulator layer (a buried oxide film layer (a BOX layer)). Therefore, effects such as a high-speed/low-power-consumption operation, prevention of a software error, and others can be expected, and this wafer appears promising as a substrate for a high-performance semiconductor device.
As a typical method for manufacturing this SOI wafer, there is a wafer bonding method or an SIMOX method. The wafer bonding method is a method of forming a thermal oxide film on, e.g., a surface of at least one of two silicon single crystal wafers, then closely attaching the two wafers to each other through the formed thermal oxide film, performing a bonding heat treatment to increase a bonding strength, and thereafter reducing a thickness of one wafer (a wafer to be a SOI layer (which will be referred to as a bond wafer)) by, e.g., mirror polishing, thereby manufacturing an SOI wafer. Further, as a method for reducing a thickness, there is, e.g., a method of grinding or polishing a bond wafer until a desired thickness is obtained, a method called an “ion implantation delamination method” of implanting at least either hydrogen ions or rare gas ions into a bond wafer to form an ion implanted layer and then delaminating the bond wafer in the ion implanted layer.
On the other hand, the SIMOX method is a method for manufacturing an SOI wafer by ion-implanting oxygen into a single-crystal silicon substrate, then performing a high-temperature heat treatment (an oxide film forming heat treatment), and reacting the implanted oxygen and silicon to form a BOX layer.
Of the two typical techniques, the wafer bonding method has the superiority that a thickness of the SOI layer or the BOX layer can be freely set, and hence this method can be applied to various device applications.
Among others, since the ion implantation delamination method can greatly improve the film thickness uniformity of the SOI layer to be fabricated, this method has been actively used in recent years.
On the other hand, to suppress warpage of an SOI wafer or improve a gettering capability, using a base wafer having boron doped at a high concentration to manufacture the SOI wafer has been often performed as described in Japanese Patent Application Laid-open No. 1993-226620 or Japanese Patent Application Laid-open No. 1996-37286.
When applying such a base wafer having boron doped at a high concentration to the ion implantation delamination method, a structure having a very thick buried insulator layer having a thickness of, e.g., 2 μm or above or 10 μm or above formed therein may be demanded. In such a case, when a thick oxide film is formed on a bond wafer to be bonded, there arises a problem that ion implantation energy must be extremely increased or warpage of an SOI wafer to be fabricated increases, and hence a thick oxide film must be formed on a base wafer side to be bonded to the bond wafer.
At this time, since the base wafer having boron doped at a high concentration is thermally oxidized to form the thick oxide film, a large amount of boron is contained in the thermal oxide film, and there occurs a problem that boron contained in a thermal oxide film on a back surface side of the SOI wafer outwardly diffuses to contaminate the SOI layer with a dopant when performing a bonding heat treatment, a flattening heat treatment, or a high-temperature heat treatment such as epitaxial growth with respect to the SOI wafer after delamination. When such auto-doping occurs, a conductivity type or a resistivity of the SOI layer changes.
The same problem occurs due to a heat treatment that performs epitaxial growth on an SOI layer after reducing a film thickness and thereby increases a film thickness of the SOI layer or a heat treatment during a device manufacturing process using an SOI wafer even though any other film thickness reducing technique such as grinding or polishing is used.